1. Field of the Invention
The present invention relates to a semiconductor storage device such as a Read Only Memory (ROM) or a flash memory constructed of a semiconductor integrated circuit (for example, a Large Scale Integration (LSI) circuit), and more particularly to disposition of a data read circuit in a serial input/output interface or the like.
2. Description of the Related Art
FIG. 1 is a schematic plan view illustrating a conventional semiconductor storage device.
For example, the serial storage device is constructed of a memory LSI chip such as a flash memory or ROM having a serial input/output interface.
Generally, the semiconductor storage device has a structure such that a memory cell array 2 for data storage occupies most of a chip 1 which is a rectangular substrate as shown in FIG. 1. That is, the memory cell array 2 is disposed at the center of the chip 1 and peripheral circuits for reading data from the memory cell array 2 (for example, an address decoder 3, an output multiplexer 4, input/output control circuits (not shown), etc.) are disposed around the memory cell array 2. In the case of a memory LSI chip, pads for input/output signals are mostly disposed on the chip 1 along two opposing sides of the chip 1. In this case, data input pads 5 for inputting address signals or the like are disposed on the chip 1 along one side (for example, a lower side in the figure) of the chip 1 and data output pads 6 for outputting data signals or the like are disposed along another side (for example, an upper side in the figure) thereof. In addition, a hold command input pad 7 for inputting a hold command is disposed on the chip 1 along the same side as where the data input pads 5 are disposed and a clock input pad 8 for inputting a clock signal or the like is disposed along the same side as where the data output pads 6 are disposed.
In the case where the semiconductor storage device is constructed as described above, the chip size thereof is determined such that the lateral length of the chip 1 is determined based on the memory cell array 2 that occupies most of the chip 1 and the longitudinal length is determined after peripheral circuits or the like are disposed as closely as possible along the lateral sides of the chip 1.
For example, Japanese Patent Kokai No. 2004-71838 describes a technology in connection with the semiconductor storage device of FIG. 1 in which address terminals are disposed on a chip along one side of the chip and data terminals are disposed along the opposite side.
However, the conventional semiconductor storage device has the following problems.
In the conventional semiconductor storage device shown in FIG. 1, the data input pads 5, the data output pads 6, and the like are disposed on the chip 1 along the two sides of the memory cell array 2. The semiconductor storage device cannot achieve required memory read performance when respective distances (i.e., lengths) of wirings between the input/output control circuit (not shown) and the data input and output pads 5 and 6 are different since memory read time is determined based on the wiring distances (i.e., based on signal delay times due to resistances of the wirings).